Die Gruppe Skalierbare Hardware-Plattformen entwickelt ein skalierbares Multiprozessorsystem (Multiprocessor System-on-Chip, MPSoC), das eine sichere und energieeffiziente Datenverarbeitung für Anwendungen des Internet der Dinge (IoT) ermöglicht. Wir untersuchen Sicherheitskonzepte in MPSoC-Architekturen, um verschiedenartige parallel ausgeführte Applikationen voneinander zu isolieren und damit die Auswirkungen von Schadsoftware oder Applikationsfehlern zu minimieren. Die Prozessorplattform stellt die notwendigen Hardwarekomponenten für ein Mikrokern-basiertes Betriebssystem bereit, welches in enger Zusammenarbeit mit der Gruppe Modulare Betriebssysteme im Forschungsthema Modularisierung von Hard- und Software integriert wird. Die Realisierung des MPSoC erfolgt als FPGA-Implementierung und als Forschungschip in Siliziumtechnologie.
Mattis Hasler, RoadRunner: A Modularized Hardware Design Management and EDA Tool Runner, Second Workshop on Open-Source Computer Architecture Research (OSCAR), 2023
@conference{
rr_hasler23,
title = "RoadRunner: A Modularized Hardware Design Management and EDA Tool Runner",
author = "Mattis Hasler",
year = "2023",
booktitle = "Second Workshop on Open-Source Computer Architecture Research (OSCAR)",
month = "June",
year = "2023"
}
Sebastian Haas, Nils Asmussen, A Trusted Communication Unit for Secure Tiled Hardware Architectures, 2022 29th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2022, Download PDF
@inproceedings{
hwtcu-haas,
title = "A Trusted Communication Unit for Secure Tiled Hardware Architectures",
author = "Sebastian Haas, Nils Asmussen",
year = "2022",
booktitle = "2022 29th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)",
month = "October",
pages = "1-4"
}
Sebastian Haas, Mattis Hasler, Friedrich Pauls, Stefan Köpsell, Nils Asmussen, Michael Roitzsch, Gerhard Fettweis, Trustworthy Computing for O-RAN: Security in a Latency-Sensitive Environment, 2nd Workshop On Architectural Evolution Toward 6G Networks - 6GARCH, 2022, Download PDF
@inproceedings{
m3oran-haas,
title = "Trustworthy Computing for O-RAN: Security in a Latency-Sensitive Environment",
author = "Sebastian Haas, Mattis Hasler, Friedrich Pauls, Stefan Köpsell, Nils Asmussen, Michael Roitzsch, Gerhard Fettweis",
year = "2022",
booktitle = "2nd Workshop On Architectural Evolution Toward 6G Networks - 6GARCH",
month = "December",
pages = "1-6"
}
Mattis Hasler, Sebastian Haas, Robert Wittig, Stefan Scholze, Andreas Dixius, Sebastian Höppner, Gerhard Fettweis, Christian Mayr, A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI, 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022, Download PDF
@inproceedings{
haslerkachel1,
title = "A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI",
author = "Mattis Hasler, Sebastian Haas, Robert Wittig, Stefan Scholze, Andreas Dixius, Sebastian Höppner, Gerhard Fettweis, Christian Mayr",
year = "2022",
booktitle = "2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)",
month = "July",
pages = "217-222",
doi = "10.1109/ISVLSI54635.2022.00050"
}
Friedrich Pauls, Sebastian Haas, Stefan Köpsell, Michael Roitzsch, Nils Asmussen, Gerhard Fettweis, On Trustworthy Scalable Hardware/Software Platform Design, Smart Systems Integration Conference and Exhibition (SSI), 2022, Download PDF
@inproceedings{
hwswplatform_pauls2022,
title = "On Trustworthy Scalable Hardware/Software Platform Design",
author = "Friedrich Pauls, Sebastian Haas, Stefan Köpsell, Michael Roitzsch, Nils Asmussen, Gerhard Fettweis",
year = "2022",
booktitle = "Smart Systems Integration Conference and Exhibition (SSI)",
month = "April"
}
Nils Asmussen, Sebastian Haas, Carsten Weinhold, Till Miemietz, Michael Roitzsch, Efficient and Scalable Core Multiplexing with M³v, ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2022, Download PDF
@inproceedings{
Asmussen:M3v,
title = "Efficient and Scalable Core Multiplexing with M³v",
author = "Nils Asmussen, Sebastian Haas, Carsten Weinhold, Till Miemietz, Michael Roitzsch",
year = "2022",
booktitle = "ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)",
address = "Lausanne, Switzerland",
month = "February",
publisher = "ACM",
pages = "452–466",
url = "https://doi.org/10.1145/3503222.3507741"
}
Sebastian Haas, Nils Asmussen, HW/SW Design Challenges for Secure Computing Platforms, HiPEAC CSW Autumn, 2021
@conference{
hipeac-csw-autumn21-bi,
title = "HW/SW Design Challenges for Secure Computing Platforms",
author = "Sebastian Haas, Nils Asmussen",
year = "2021",
booktitle = "HiPEAC CSW Autumn",
address = "Lyon, France",
month = "October",
note = "Presentation",
url = "https://www.youtube.com/watch?v=pn9mmnWfvQE"
}
Gerhard Fettweis, Mattis Hasler, Robert Wittig, Emil Matus, Stefan Damjancevic, Sebastian Haas, Friedrich Pauls, Seungseok Nam, Nairuhi Grigoryan, A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel, 2019 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
@inproceedings{
9048785,
title = "A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel",
author = "Gerhard Fettweis, Mattis Hasler, Robert Wittig, Emil Matus, Stefan Damjancevic, Sebastian Haas, Friedrich Pauls, Seungseok Nam, Nairuhi Grigoryan",
year = "2019",
booktitle = "2019 53rd Asilomar Conference on Signals, Systems, and Computers",
pages = "896-900",
url = "https://ieeexplore.ieee.org/abstract/document/8920308",
doi = "10.1109/IEEECONF44664.2019.9048785"
}
Gerhard Fettweis, Emil Matus, Robert Wittig, Mattis Hasler, Stefan Damjancevic, Seungseok Nam, Sebastian Haas, 5G-and-Beyond Scalable Machines, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019
@inproceedings{
8920308,
title = "5G-and-Beyond Scalable Machines",
author = "Gerhard Fettweis, Emil Matus, Robert Wittig, Mattis Hasler, Stefan Damjancevic, Seungseok Nam, Sebastian Haas",
year = "2019",
booktitle = "2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)",
pages = "105-109",
url = "https://ieeexplore.ieee.org/abstract/document/8920308",
doi = "10.1109/VLSI-SoC.2019.8920308"
}
Friedrich Pauls, Robert Wittig, Gerhard Fettweis, A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet, Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
@inproceedings{
10.1007/978-3-030-27562-4_7,
title = "A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet",
author = "Friedrich Pauls, Robert Wittig, Gerhard Fettweis",
year = "2019",
booktitle = "Embedded Computer Systems: Architectures, Modeling, and Simulation",
publisher = "Springer International Publishing",
pages = "93-106"
}