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Barkhausen Institut

Scalable Computing Hardware

The group Scalable Computing Hardware develops a scalable multiprocessor system-on-chip (MPSoC) which enables secure and energy-efficient data processing for applications of the internet of things (IoT). We investigate security concepts in MPSoC architectures to isolate various parallel applications and to minimize the impact of malicious attacks or software faults. The processor platform provides the necessary hardware components for a microkernel-based operating system which will be integrated in close collaboration with the group Composable Operating Systems within the research topic Composability of Hardware and Software. The MPSoC is realized as FPGA implementation as well as a silicon research chip.

Who we are

Sebastian Haas
Dr.-Ing.Sebastian HaasResearch Associate
Mattis Hasler
Dipl.-Ing.Mattis HaslerResearch Associate
Friedrich Pauls
Dr.-Ing.Friedrich PaulsResearch Associate

Publications

Friedrich Pauls, Robert Wittig, Gerhard Fettweis, A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet, Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

@inproceedings{
10.1007/978-3-030-27562-4_7,
title = "A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet",
author = "Friedrich Pauls, Robert Wittig, Gerhard Fettweis",
year = "2019",
booktitle = "Embedded Computer Systems: Architectures, Modeling, and Simulation",
publisher = "Springer International Publishing",
pages = "93-106"
}
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Gerhard Fettweis, Emil Matus, Robert Wittig, Mattis Hasler, Stefan Damjancevic, Seungseok Nam, Sebastian Haas, 5G-and-Beyond Scalable Machines, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019

@inproceedings{
8920308,
title = "5G-and-Beyond Scalable Machines",
author = "Gerhard Fettweis, Emil Matus, Robert Wittig, Mattis Hasler, Stefan Damjancevic, Seungseok Nam, Sebastian Haas",
year = "2019",
booktitle = "2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)",
pages = "105-109",
url = "https://ieeexplore.ieee.org/abstract/document/8920308",
doi = "10.1109/VLSI-SoC.2019.8920308"
}
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Gerhard Fettweis, Mattis Hasler, Robert Wittig, Emil Matus, Stefan Damjancevic, Sebastian Haas, Friedrich Pauls, Seungseok Nam, Nairuhi Grigoryan, A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel, 2019 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

@inproceedings{
9048785,
title = "A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel",
author = "Gerhard Fettweis, Mattis Hasler, Robert Wittig, Emil Matus, Stefan Damjancevic, Sebastian Haas, Friedrich Pauls, Seungseok Nam, Nairuhi Grigoryan",
year = "2019",
booktitle = "2019 53rd Asilomar Conference on Signals, Systems, and Computers",
pages = "896-900",
url = "https://ieeexplore.ieee.org/abstract/document/8920308",
doi = "10.1109/IEEECONF44664.2019.9048785"
}
Download BibTex