Masur chip series
Technical details of the platform
Masur is a secure, scalable SoC platform designed to get your IP to silicon quickly.
- Masur enables the co-integration of
multiple IPs - Masur provides a communication and
software platform for building a
demonstrator - Masur facilitates the seamless integration
of your IP thanks to a comprehensive
range of integration toolsand interfaces,
as well as a suitable software stack
Cost-effective integration of your IP
Masur combines multiple IP on a multiproject chip to reduce integration costs.
The multi-project chip is made possible by the isolation-by-default design of the Masur platform,
a hardware/software co-design featuring a tilebased architecture and a microkernel operating system.
Comprehensive integration environment
The integration environment supports you throughout the various phases of your project. Our toolchain enables you to perform requirements
analysis in software using our Masur models within the gem5 system simulator. Our Masur IP is also available as an FPGA implementation. This allows you to implement the Masur design entirely within your own FPGA, enabling integration into silicon with little or no modification.
Our services
- We integrate RTL designs, post-placeand-route netlists and analogue IP
- We provide an integration environment that allows you to turn your idea into a chip step by step – from system simulation in gem5, through initial steps with the Masur FPGA platform on your own FPGA boards, to co-integration in one of our chip tape-outs
- We offer the Accelerator Support Module on RISC-V 32-bit as soft IP for accelerators
- We offer a complete chip tape-out including remote access to the finished PCB